On-chip versus off-chip test: an artificial dichotomy

There has been some recent interest in the subject of whether circuits should be tested with built-in self-test (BIST) or automated test equipment (ATE). As with many such debates, neither extreme is a viable position, and the true answer lies somewhere in the middle. BIST patterns have their place with scan patterns, IDDQ patterns, etc. as part of a test program driven by ATE. 1. " Putting a tester on the chip is too expensive " : This argument has several flavors, but the essence of it is that silicon is expensive, and adding more of it strictly for test purposes is wasteful and less cost effective than putting the same circuitry in ATE. The argument assumes that the on-chip vs. off-chip tradeoff is possible, but this is not always true. Scan design is a counterexample: it is impossible to devote a tester channel to each flip-flop, but having such access greatly simplifies test generation and improves test quality. Test structures (in the form of scan chains) are added to the chip. There is silicon overhead associated with this, but the cost of the silicon is more than offset by improvements in time-to-market, chip quality, etc. In addition, the silicon cost of making structures visible to an off-chip ATE must be considered. This issue is the main driving force behind BIST for embedded memories. A second issue is overall timing accuracy (OTA). Currently, OTA is around 200ps for testers with about a 2ns cycle time. Accounting for the OTA requires guard-banding in the test program, which results in rejecting some parts which actually meet the timing spec in order to avoid passing parts that don't. The cost of this yield loss needs to be compared with the cost of adding appropriate generation and strobe circuitry to the chip. The tradeoff looks even more promising for BIST in the future given that the SIA roadmap projects that OTA will not be able to keep pace with system clocks speeds [1]. 2. " BIST can only apply patterns and cannot vary voltage or apply precision measurements the way ATE can " : This argument only applies if BIST is to be the sole test method and applied without conventional ATE. If ATE is to be used to apply the BIST, then BIST vectors can be run at a variety of voltages, and at whatever temperature is supported by the ATE environment. The …